What are the questions asked in GATE 2018 Electronics and Communication Engineering exam?

Complete set of questions from GATE 2018 ECE exam covering Network Theory, Analog Circuits, Digital Electronics, Signals and Systems, Control Systems, Communication Systems, Electromagnetic Theory, Electronic Devices, and more with detailed solutions.

Where can I download GATE 2018 Electronics and Communication question paper?

You can download the complete GATE 2018 Electronics and Communication Engineering question paper with solutions from ExamPrev. The PDF includes all questions with detailed explanations.

How many questions were in GATE 2018 ECE paper?

GATE 2018 Electronics and Communication Engineering paper consisted of 65 questions including MCQs, MSQs, and numerical answer type questions covering all major ECE topics.

Are solutions provided for GATE 2018 ECE questions?

Yes, detailed step-by-step solutions with explanations are provided for all questions from GATE 2018 Electronics and Communication Engineering paper.

What topics are covered in GATE 2018 ECE paper?

GATE 2018 ECE covers Network Theory, Electronic Devices, Analog Circuits, Digital Electronics, Signals and Systems, Control Systems, Communication Systems, Electromagnetic Theory, Microprocessors, VLSI Design, and Engineering Mathematics.

Electronics and Communication Gate 2018 Questions with Answer

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Ques 1 GATE 2018

Consider the following amplitude modulated signal: s(t)=cos(2000πt)+4cos(2400πt)+cos(2800πt). The ratio (accurate to three decimal places) of the power of the message signal to the power of the carrier signal is

(0.125) is the correct answer.

Ques 2 GATE 2018

Let c(t)=A_ccos(2πf_ct) and m(t)=cos(2πf_mt) It is given that f_c>>5f_m. The signal c(t)+m(t) is applied to the input of a non-linear device, whose output v_o(t) is related to the input v_i(t) as v_o(t)=av_i(t)+bv_i²(t), where a and b are positive constants. The output of the non-linear device is passed through an ideal band-pass filter with center frequency f_c and bandwidth 3f_m, to produce an amplitude modulated (AM) wave. If it is desired to have the sideband power of the AM wave to be half of the carrier power, then a/b is

0.25

0.5

(d) is the correct answer.

Ques 3 GATE 2018

Let the input be u and the output be y of a system, and the other parameters are real constants. Identify which among the following systems is not a linear system:

d³y/dt³+a₁d²y/dt²+a₂dy/dt+a₃y=b₃u+b₂du/dt+b₁d²u/dt² (with initial rest conditions)

y(τ)=∫₀^te^α(τ-τ)βu(τ)dτ

y=au+b, b≠0

y=au

Ques 4 GATE 2018

The Nyquist stability criterion and the Routh criterion both are powerful analysis tools for determining the stability of feedback controllers. Identify which of the following statements is FALSE:

Both the criteria provide information relative to the stable gain range of the system.

The general shape of the Nyquist plot is readily obtained from the Bode magnitude plot for all minimum-phase systems.

The Routh criterion is not applicable in the condition of transport lag, which can be readily handled by the Nyquist criterion.

The closed-loop frequency response for a unity feedback system cannot be obtained from the Nyquist plot.

(d) is the correct answer.

Ques 5 GATE 2018

The state equation and the output equation of a control system are given below:

The transfer function representation of the system is

(3s+5)/(s²+4s+6)

(3s-1.875)/(s²+4s+6)

(4s+1.5)/(s²+4s+6)

(6s+5)/(s²+4s+6)

(a) is the correct answer.

Ques 6 GATE 2018

For a unity feedback control system with the forward path transfer function G(s)=K/s(s+2). The peak resonant magnitude M_r of the closed-loop frequency response is 2. The corresponding value of the gain K (correct to two decimal places) is

(15) is the correct answer.

Ques 7 GATE 2018

The figure below shows the Bode magnitude and phase plots of a stable transfer function G(s)=n₀/(s³+d₂s²+d₁s+d₀). Consider the negative unity feedback configuration with gain k in the feedforward path.

The closed loop is stable for k0. The maximum value of k₀ is

(0.1) is the correct answer.

Ques 8 GATE 2018

The logic function f(X,Y) realized by the given circuit is

NOR

AND

NAND

XOR

(d) is the correct answer.

Ques 9 GATE 2018

A function F(A,B,C) defined by three Boolean variables A, B and C when expressed as sum of products is given by F=Ā·B̄·C̄+Ā·B·C̄+A·B̄·C̄ where, Ā, B̄, and C̄ are the complements of the respective variables. The product of sums (POS) form of the function F is

F=(A+B+C)·(A+B̄+C)·(Ā+B+C)

F=(Ā+B̄+C̄)·(Ā+B+C̄)·(A+B̄+C̄)

F=(A+B+C̄)·(A+B̄+C̄)·(Ā+B+C̄)·(Ā+B̄+C)·(Ā+B̄+C̄)

F=(Ā+B̄+C)·(Ā+B+C)·(A+B̄+C)·(A+B̄+C)·(A+B+C̄)·(A+B+C)

Ques 10 GATE 2018

A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is

(5) is the correct answer.

Ques 11 GATE 2018

A four-variable Boolean function is realized using 4×1 multiplexers as shown in the figure. The minimized expression for F(U,V,W,X) is

(UV+ŪV̄)W̄

(UV+ŪV̄)(W̄X̄+W̄X)

(UV̄+ŪV)W̄

(UV̄+ŪV)(W̄X̄+W̄X)

Ques 12 GATE 2018

A 2x2 ROM array is built with the help of diodes as shown in the circuit below. Here WO and W1 are signals that select the word lines and BO and B1 are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation.

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to D_ij (where i=0 or 1 and j=0 or 1) stored in the ROM?

[[1,0],[0,1]]

[[0,1],[1,0]]

[[1,0],[1,0]]

[[1,1],[0,0]]

(a) is the correct answer.

Ques 13 GATE 2018

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data D_in using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of ΔT/T_CK=0.15, where the parameters ΔT and T_CK are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

If the probability of input data bit (D_in) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node X, is

(0.84) is the correct answer.

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