Electronics and Communication GATE 2017 Set-1 Questions with Answer

Ques 1 Control Systems

A linear time invariant (LTI) system with the transfer function G(s)=K(s²+2s+2)/(s²-3s+2) is connected in unity feedback configuration as shown in the figure.

Ques 2 Control Systems

Which one of the following options correctly describes the locations of the roots of the equation s⁴+s²+1=0 on the complex plane?

Ques 3 Control Systems

The Nyquist plot of the transfer function G(s)=K/((s²+2s+2)(s+2)) does not encircle the point (-1+j0) for K=10 but does encircle the point (-1+j0) for K=100 Then the closed loop system (having unity gain feedback) is

Ques 4 Control Systems

The open loop transfer function G(s)=(s+1)/(s^p(s+2)(s+3)) where p is an integer, is connected in unity feedback configuration as shown in the figure.

Ques 5 Control Systems

Consider a stable system with transfer function G(s)=(s^p+b₁s^p-1+...+b_p)/(s^q+a₁s^q-1+...+a_q) where b₁,...,b_p and a₁,...,a_q are real valued constants. The slope of the Bode log magnitude curve of G(s) converges to -60 dB/decade as ω→∞. A possible pair of values for p and q is

Ques 6 Control Systems

Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?

Ques 7 Digital Circuits

Which one of the following gives the simplified sum of products expression for the Boolean function F=m₀+m₂+m₃+m₅ where m₀, m₂, m₃ and m₅ are minterms corresponding to the inputs A, B and C with A as the MSB and C as the LSB?

Ques 8 Digital Circuits

A 4-bit shift register circuit configured for right-shift operation. i.e. D_in→A, A→B, B→C, C→D. is shown. If the present state of the shift register is ABCD=1101 the number of clock cycles required to reach the state ABCD=1111 is

Ques 9 Digital Circuits

A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are Q_AQ_B=00,01,10, and 11.

Ques 10 Digital Circuits

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P=Q='0'. If the input condition is changed simultaneously to P=Q='1' the outputs X and Y are

Ques 11 Digital Circuits

Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1.

Ques 12 Digital Communication

In binary frequency shift keying (FSK), the given signal waveforms are u₀(t)=5cos(20000πt);0≤t≤T, and u₁(t)=5cos(22000πt);0≤t≤T, where T is the bit-duration interval and t is in seconds. Both u₀(t) and u₁(t) are zero outside the interval 0≤t≤T. With a matched filter (correlator) based receiver, the smallest positive value of T (in milliseconds) required to have u₀(t) and u₁(t) uncorrelated is

Ques 13 Digital Communication

Which one of the following statements about differential pulse code modulation (DPCM) is true?