Electronics and Communication Gate 2017 Set-1 Questions with Answer

Ques 1 GATE 2017 SET-1

A linear time invariant (LTI) system with the transfer function G(s)=K(s²+2s+2)/(s²-3s+2) is connected in unity feedback configuration as shown in the figure.

For the closed loop system shown, the root locus for 0

K>1.5

no positive value of K

(a) is the correct answer.

Ques 2 GATE 2017 SET-1

Which one of the following options correctly describes the locations of the roots of the equation s⁴+s²+1=0 on the complex plane?

Four left half plane (LHP) roots

One right half plane (RHP) root, one LHP root and two roots on the imaginary axis

Two RHP roots and two LHP roots

All four roots are on the imaginary axis

Ques 3 GATE 2017 SET-1

The Nyquist plot of the transfer function G(s)=K/((s²+2s+2)(s+2)) does not encircle the point (-1+j0) for K=10 but does encircle the point (-1+j0) for K=100 Then the closed loop system (having unity gain feedback) is

stable for K=10 and stable for K=100

stable for K=10 and unstable for K=100

unstable for K=10 and stable for K=100

unstable for K=10 and unstable for K=100

(b) is the correct answer.

Ques 4 GATE 2017 SET-1

The open loop transfer function G(s)=(s+1)/(s^p(s+2)(s+3)) where p is an integer, is connected in unity feedback configuration as shown in the figure.

Given that the steady state error is zero for unit step input and is 6 for unit ramp input, the value of the parameter p is

(1) is the correct answer.

Ques 5 GATE 2017 SET-1

Consider a stable system with transfer function G(s)=(s^p+b₁s^p-1+...+b_p)/(s^q+a₁s^q-1+...+a_q) where b₁,...,b_p and a₁,...,a_q are real valued constants. The slope of the Bode log magnitude curve of G(s) converges to -60 dB/decade as ω→∞. A possible pair of values for p and q is

p=0 and q=3

p=1 and q=7

p=2 and q=3

p=3 and q=5

(a) is the correct answer.

Ques 6 GATE 2017 SET-1

Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?

(a) is the correct answer.

Ques 7 GATE 2017 SET-1

Which one of the following gives the simplified sum of products expression for the Boolean function F=m₀+m₂+m₃+m₅ where m₀, m₂, m₃ and m₅ are minterms corresponding to the inputs A, B and C with A as the MSB and C as the LSB?

ĀB+ĀB̄C̄+A B̄C

ĀC̄+ĀB+A B̄C

ĀC̄+A B̄+A B̄C

ĀBC+ĀC̄+A B̄C

(b) is the correct answer.

Ques 8 GATE 2017 SET-1

A 4-bit shift register circuit configured for right-shift operation. i.e. D_in→A, A→B, B→C, C→D. is shown. If the present state of the shift register is ABCD=1101 the number of clock cycles required to reach the state ABCD=1111 is

(10) is the correct answer.

Ques 9 GATE 2017 SET-1

A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are Q_AQ_B=00,01,10, and 11.

Assume that X_IN is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state Q_AQ_B=00 and clocked, after a few clock cycles, it starts cycling through

all of the four possible states if X_IN=1

three of the four possible states if X_IN=0

only two of the four possible states if X_IN=1

only two of the four possible states if X_IN=0

(d) is the correct answer.

Ques 10 GATE 2017 SET-1

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P=Q='0'. If the input condition is changed simultaneously to P=Q='1' the outputs X and Y are

X='1', Y='1'

either X='1', Y='0' or X='0', Y='1'

either X='1', Y='1' or X='0', Y='0'

X='0', Y='0'

(b) is the correct answer.

Ques 11 GATE 2017 SET-1

Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1.

The duty cycle at the output of the latch in percentage is

(30) is the correct answer.

Ques 12 GATE 2017 SET-1

In binary frequency shift keying (FSK), the given signal waveforms are u₀(t)=5cos(20000πt);0≤t≤T, and u₁(t)=5cos(22000πt);0≤t≤T, where T is the bit-duration interval and t is in seconds. Both u₀(t) and u₁(t) are zero outside the interval 0≤t≤T. With a matched filter (correlator) based receiver, the smallest positive value of T (in milliseconds) required to have u₀(t) and u₁(t) uncorrelated is

0.25 ms

0.5 ms

0.75 ms

1.0 ms

(b) is the correct answer.

Ques 13 GATE 2017 SET-1

Which one of the following statements about differential pulse code modulation (DPCM) is true?

The sum of message signal sample with its prediction is quantized

The message signal sample is directly quantized, and its prediction is not used

The difference of message signal sample and a random signal is quantized

The difference of message signal sample with its prediction is quantized

(d) is the correct answer.

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