Electronics & Communication Gate Yearwise
Electronics and Communication GATE 2016 Set-2 Questions with Answer
Ques 1 Control Systems
The response of the system G(s)=(s-2)/((s+1)(s+3)) to the unit step input u(t) is y(t). The value of dy/dt at t=0+ is
1 is the correct answer.
Ques 2 Control Systems
The number and direction of encirclements around the point -1+j0 in the complex plane by the Nyquist plot of G(s)=(1-s)/(4+2s) is
Ques 3 Control Systems
In the feedback system shown below G(s)=1/(s2+2s). The step response of the closed-loop system should have minimum settling time and have no overshoot.

1 is the correct answer.
Ques 4 Control Systems
In the feedback system shown below G(s)=1/((s+1)(s+2)(s+3)).

60 is the correct answer.
Ques 5 Control Systems
The asymptotic Bode phase plot of G(s)=k/((s+0.1)(s+10)(s+p1)) with k and p1 both positive, is shown below.

1 is the correct answer.
Ques 6 Digital Circuits
Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

Ques 7 Digital Circuits
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R=10 kΩ and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

1.5 is the correct answer.
Ques 8 Digital Circuits
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cin is the input carry and Cout is the output carry. A and B are to be used as the select bits with A being the more significant select bit.

Ques 9 Digital Circuits
In an N bit flash ADC, the analog voltage is fed simultaneously to 2N comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source Vin (whose output is being converted to digital format) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full scale input change for proper conversion. Assume that the time taken by the thermometer to binary encoder is negligible. If the flash ADC has 8 bit resolution,

Ques 10 Digital Circuits
The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is shown in the figure.

Ques 11 Digital Communication
A discrete memoryless source has an alphabet {a1, a2, a3, a4} with corresponding probabilities {1/2, 1/4, 1/8, 1/8}. The minimum required average codeword length in bits to represent this source for error-free reconstruction is
1.75 is the correct answer.
Ques 12 Digital Communication
A speech signal is sampled at 8 kHz and encoded into PCM format using 8 bits/sample. The PCM data is transmitted through a baseband channel via 4-level PAM. The minimum bandwidth (in kHz) required for transmission is
16 is the correct answer.
Ques 13 Digital Communication
An information source generates a binary sequence {αn}. αn can take one of the two possible values -1 and +1 with equal probability and are statistically independent and identically distributed. This sequence is precoded to obtain another sequence {βn}, as βn=αn+kαn-3. The sequence {βn} is used to modulate a pulse g(t) to generate the baseband signal X(t)=∑n=-∞∞βng(t-nT), where g(t)=1, 0≤t≤T and 0, otherwise. If there is a null at f=1/(3T) in the power spectral density of X(t), then k is
-1 is the correct answer.

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