Electronics & Communication Gate Yearwise
Electronics and Communication GATE 2025 Questions with Answer
Ques 14 Control Systems
Consider the unity-negative-feedback system shown in Figure (i) below, where gain K≥0. The root locus of this system is shown in Figure (ii) below.
For what value(s) of K will the system in Figure (i) have a pole at -1+j1?
Ques 15 Control Systems
Let G(s)=1/(10s2) be the transfer function of a second-order system. A controller M(s) is connected to the system G(s) in the configuration shown below.
Consider the following statements.
(i) There exists no controller of the form M(s)=KI/s, where KI is a positive real number, such that the closed loop system is stable.
(ii) There exists at least one controller of the form M(s)=KP+sKD, where KP and KD are positive real numbers, such that the closed loop system is stable.
Which one of the following options is correct?
Ques 16 Control Systems
Consider the polynomial p(s)=s5+7s4+3s3-33s2+2s-40. Let (L, I, R) be defined as follows.
L is the number of roots of p(s) with negative real parts.
I is the number of roots of p(s) that are purely imaginary.
R is the number of roots of p(s) with positive real parts.
Which one of the following options is correct?
Ques 17 Control Systems
Consider a system where x1(t), x2(t), and x3(t) are three internal state signals and u(t) is the input signal. The differential equations governing the system are given by
Ques 18 Control Systems
Consider a system represented by the block diagram shown below. Which of the following signal flow graphs represent(s) this system? Choose the correct option(s).
Ques 19 Digital Logic
A 3-input majority logic gate has inputs X, Y, and Z. The output F of the gate is logic '1' if two or more of the inputs are logic '1'. The output F is logic '0' if two or more of the inputs are logic '0'.
Which one of the following options is a Boolean expression of the output F?
Ques 20 Digital Logic
A full adder and an XOR gate are used to design a digital circuit with inputs X, Y, and Z, and output F, as shown below. The input Z is connected to the carry-in input of the full adder.
If the input Z is set to logic '1', then the circuit functions as ______ with X and Y as inputs.
Ques 21 Digital Logic
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input PO is set to logic '0' and P1 is set to logic '1' at all times. The timing diagram of the inputs SEL and S are also shown below.
The sequence of output Y from time T0 to T3 is
Ques 22 Digital Logic
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns.
The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is
Ques 23 Electromagnetics
A square metal sheet of 4m × 4m is placed on the x-y plane as shown in the figure below.
If the surface charge density (in μC/m2) on the sheet is ρs(x,y)=4|y|, then the total charge (in μC, rounded off to the nearest integer) on the sheet is
Ques 24 Electromagnetics
An electric field of 0.01 V/m is applied along the length of a copper wire of circular cross-section with diameter 1 mm. Copper has a conductivity of 5.8×107 S/m.
The current (in Amperes, rounded off to two decimal places) flowing through the wire is
Ques 25 Electromagnetics
A 50 Ω lossless transmission line is terminated with a load ZL of (50-j75) Ω.
If the average incident power on the line is 10 mW, then the average power delivered to the load (in mW, rounded off to one decimal place) is
Ques 26 Electronic Devices and Circuits
A simplified small-signal equivalent circuit of a BJT-based amplifier is given below.
The small-signal voltage gain Vo/VS (in V/V) is
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