Digital Logic Design GATE CS and IT previous year questions with Answer

Ques 21 Gate 2016 Set-2

Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _____________

Ques 22 Gate 2016 Set-2

Let, x₁⊕x₂⊕x₃⊕x₄= 0 where x₁, x₂, x₃, x₄ are Boolean variables, and ⊕ is the XOR operator. Which one of the following must always be TRUE ?

Ques 23 Gate 2016 Set-1

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is

Ques 24 Gate 2016 Set-1

The 16-bit 2’s complement representation of an integer is 1111 1111 1111 0101; its decimal representation is

Ques 25 Gate 2016 Set-1

Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

Ques 26 Gate 2016 Set-1

Consider the Boolean operator # with the following properties:

x#0 = x, x#1 = x', x#x = 0 and x#x'= 1

Then x#y is equivalent to

Ques 27 Gate 2015 Set-2

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,...) is ________

Ques 28 GATE 2015 SET-2

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.

Ques 29 Gate 2015 Set-1

Consider a 4 bit Johnson counter with an initial value of 0000. The counting sequence of this counter is

Ques 30 Gate 2015 Set-1

Which one of the following is NOT equivalent to p ↔ q?