CS/IT Gate Subject



Digital Logic Design GATE CS and IT previous year questions with Answer


Ques 11 GATE 2021 SET-1

Let the representation of a number in base 3 be 210. What is the hexadecimal representation of the number?

A

15

B

588

C

D2

D

528



Ques 12 Gate 2020

If there are m input lines n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m+n is ________ .


1024 is the correct answer.


Ques 13 Gate 2019

In 16-bit 2’s complement representation, the decimal number −28 is:

A

1111 1111 0001 1100

B

0000 0000 1110 0100

C

1111 1111 1110 0100

D

1000 0000 1110 0100



Ques 14 Gate 2019

What is the minimum number of 2-input NOR gates required to implement 4-variable function expressed in sum-of-minterms from as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available. Answer ________


3 is the correct answer.


Ques 15 Gate 2019

Two numbers are chosen independently and uniformly at random from the set {1, 2, ..., 13}. The probability (rounded off to 3 decimal places) that their 4-bit (unsigned) binary representations have the same most significant bit is ___________.


a is the correct answer.


Ques 16 Gate 2018

Consider the minterm list form of a Boolean function F given below.

F(P, Q, R, S) = Σm(0, 2, 5, 7, 9, 11) + d(3, 8, 10, 12, 14)


Here, m denotes a minterm and d denotes a don^^t care term. The number of essential prime implicants of the function F is ______ .


a is the correct answer.


Ques 17 Gate 2017 Set-2

Given the following binary number in 32 bit (single precision) IEEE-754 format:

00111110011011010000000000000000

The decimal value closest to this floating-point number is:

A

1.45 X 101

B

1.45 X 10-1

C

2.27 X 10-1

D

2.27 X 101



Ques 18 Gate 2017 Set-1

When two 8-bit numbers A7 ... A0 and B7 ... B0 in 2^^s complement representation (with A0 and B0 as the least significant bits) are added using ripple-carry adder. the sum bits obtained are S7 ... S0 and the carry bits are C7 ... C0. An overflow is said to have occurred if

A

the carry bit C7 is 1

B

all the carry bits (C7, ... , C0 ) are 1

C

(A7 . B7 . S7' + A7' . B7' . S7) is 1

D

(A0 . B0 . S0' + A0' . B0' . S0) is 1



Ques 19 Gate 2016 Set-2

The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is ____________ bits.


a is the correct answer.


Ques 20 Gate 2016 Set-2

Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation. Then X −Y is _________


a is the correct answer.