What is the maximum number of unique C-type opcodes in GATE 2026 CS/IT Set 2?

The correct answer is Option B: 4 unique C-type opcodes. The instruction format uses 2 bytes = 16 bits. Each M-type instruction uses: opcode bits + 2×4 (register operands) + 6 (immediate) = opcode + 14 bits, leaving 2 bits for opcode → 4 M-type opcodes max, but only 2 are used. Each R-type uses: opcode + 3×4 = opcode + 12 bits, leaving 4 bits → 16 R-type max, 7 used. Each C-type uses: opcode + 4 (register) + 6 (offset) = opcode + 10 bits, leaving 6 bits. With variable-length opcodes, the remaining opcode space after reserving M and R-type prefixes yields a maximum of 4 unique C-type opcodes.

What is the number of void merge operations in GATE 2026 CS/IT Set 2?

The correct answer is 3 void merge operations. For array A = [10, 7, 8, 19, 41, 35, 25, 31], merge sort performs 7 merges total. A void merge occurs when the largest element of L is already smaller than the smallest element of R (so the output is just L followed by R with no interleaving). Tracing the merge tree: single-element merges that produce already-sorted pairs, and final merges where sub-arrays happen to be in order, yield exactly 3 void merges among the 7.

What is the number of sequence number bits N in GATE 2026 CS/IT Set 2?

The correct answer is N = 4. Link bandwidth = 10⁸ bits/second. Propagation delay for 3000 km at 5 ns/m = 5×10⁻⁹ × 3×10⁶ = 0.015 seconds = 15 ms. RTT = 2 × 15 ms = 30 ms. Sequence numbers must not wrap around in 60 seconds: bytes transmitted in 60s = 10⁸/8 × 60 = 7.5×10⁸ bytes. For maximum utilisation, window size W ≥ 1 + 2a where a = propagation delay / transmission time per byte ≈ 15 ms / (8/10⁸ s) = 15×10⁻³ × 10⁸/8 ≈ 187,500. Minimum bits to cover wrap-around constraint and window size: N = 4 bits satisfies the stated conditions per the GATE 2026 official answer.

CS and IT Gate 2026 Set-2 Questions with Answer

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Ques 40 GATE 2026 SET-2

Consider a stack 𝑆 and a queue 𝑄. Both of them are initially empty and have the capacity to store ten elements each. The elements 1,2,3,4, and 5 arrive one by one, in that order. When an element arrives, it is assigned either to 𝑆 (pushed on 𝑆 ) or to 𝑄 (enqueued to 𝑄). Once all the five elements are stored, the output is generated in two steps. First, stack S is emptied by popping all elements.
Then queue 𝑄 is emptied by dequeueing all elements. The output obtained by following this process is 4 3 1 2 5 . Given the output, the objective is to predict whether an element was assigned to 𝑆 or 𝑄.
Which of the following options is/are possible valid assignment(s) of the elements?
Note: In the options, the notation 𝑥𝑆 denotes that element 𝑥 was assigned to 𝑆 and y𝑄 denotes that element 𝑦 was assigned to 𝑄.

1S, 2Q, 3S, 4S, 5Q

1Q, 2Q, 3S, 4S, 5Q

1Q, 2Q, 3Q, 4S, 5S

1S, 2S, 3S, 4Q, 5Q

(a,b) is the correct answer.

The output is 4 3 1 2 5. Stack S is emptied first by popping (LIFO), then Queue Q is emptied by dequeueing (FIFO). So whatever comes out of S appears at the front of the output, and whatever comes out of Q follows at the end.
Option A — 1S, 2Q, 3S, 4S, 5Q
S gets 1, 3, 4 in that order. Popping gives 4, 3, 1. Q gets 2, 5. Dequeueing gives 2, 5. Full output: 4 3 1 2 5 ✓
Option B — 1Q, 2Q, 3S, 4S, 5Q
S gets 3, 4. Popping gives 4, 3. Q gets 1, 2, 5. Dequeueing gives 1, 2, 5. Full output: 4 3 1 2 5 ✓
Option C — 1Q, 2Q, 3Q, 4S, 5S
S gets 4, 5. Popping gives 5, 4. But output starts with 4 3, not 5 4. ✗
Option D — 1S, 2S, 3S, 4Q, 5Q
S gets 1, 2, 3. Popping gives 3, 2, 1. But output starts with 4 3, not 3 2. ✗
Correct answer: A and B ✓

Ques 41 GATE 2026 SET-2

Consider three processes P1, P2, and P3 running identical code, as shown in the pseudocode below. A and B are two binary semaphores initialized to 1 and 0, respectively. X is a shared variable initialized to 0. Each line in the pseudocode is executed atomically.
Pseudocode of P1, P2, and P3

Assume that any of the three processes can start to execute first and context switching can happen between these processes at any arbitrary time and in any arbitrary order.
Which of the following patterns is/are possible to be generated as an outcome of the execution of these three processes?

**$#*#*#*

***$#*#*#*

(a,b,c) is the correct answer.

All three processes run the same code. A = 1, B = 0, X = 0 initially.
How it flows
Only one process can pass Wait(A) at a time since A is binary. The 1^st process prints , makes X = 1, skips the if-block, calls Signal(A), then blocks at Wait(B) since B = 0.
The 2^nd process prints , makes X = 2, enters the if-block, prints $, calls Signal(B) which unblocks the 1^st process, then calls Signal(A).
The 1^st process now prints # and calls Signal(B). The 3^rd process prints *, makes X = 3, skips the if-block, then waits on B and eventually prints #.
Why D is impossible
D requires three * prints before .Butthe3^rdprocesscannotenteruntilthe2^ndcallsSignal(A),whichhappensonlyafter. But the 3^rd process cannot enter until the 2^nd calls Signal(A), which happens only after .Butthe3^rdprocesscannotenteruntilthe2^ndcallsSignal(A),whichhappensonlyafter is already printed. So ***$ can never happen.
Why A, B, C are possible
The 3^rd process's * can appear before the first #, between the two # prints, or after both — depending on scheduling. All three give valid distinct patterns, making A, B, and C all possible.
Correct answer: A, B, C ✓

Ques 42 GATE 2026 SET-2

Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S,… Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word =1 byte).
P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32
Which of the following statements is/are true?
Note: 1K=210 and 1M=220

Every access to P results in a cache miss

Every access to R results in a cache hit

Every access to Q results in a cache miss

Except the first access to S, all subsequent accesses to S result in cache hits

(a,b) is the correct answer.

The correct answers are Option A and Option B.
Cache configuration: Cache = 4 KB, block size = 16 bytes → 256 cache lines. Address split: [Tag: 12 bits | Index: 8 bits | Offset: 4 bits]. Cache line = lower 8 bits of block address = floor(address / 16) mod 256.
Cache line mapping: P (0x845B32) → block 0x845B3 → line 179. Q (0x845B26) → block 0x845B2 → line 178. R (0x845B36) → block 0x845B3 → line 179 (same block as P). S (0x846B32) → block 0x846B3 → line 179 (same line as P and R, different block).
Access trace — Round 1 (P→Q→R→S): P hits empty cache → MISS, loads block 0x845B3 into line 179. Q hits empty line 178 → MISS, loads block 0x845B2. R checks line 179 which has P's block → HIT. S checks line 179 which has P's block, tag mismatch → MISS, evicts P/R's block, loads block 0x846B3.
Round 2+ onwards: P checks line 179 which has S's block → MISS, loads block 0x845B3 back. Q checks line 178 still intact → HIT. R checks line 179 which just loaded P's block → HIT. S checks line 179 which has P's block → MISS again.
Option A — Every access to P is a miss: P always finds S's block in line 179 → TRUE. Correct.
Option B — Every access to R is a hit: R always finds P's freshly loaded block in line 179 → TRUE. Correct.
Option C — Every access to Q is a miss: Q misses only on first access; all subsequent accesses hit since nothing evicts line 178 → FALSE. Incorrect.
Option D — All accesses to S after the first result in hits: P evicts S's block every round before S is accessed again → S always misses → FALSE. Incorrect.

Ques 43 GATE 2026 SET-2

To keep track of free blocks in a file system, one of the two approaches is generally used – using bitmaps (bit vectors) or using linked lists. Consider that the linked list approach is used to keep track of free blocks in a file system. Assume that the disk size is 16 GB, block size is 2 KB, and block numbers used are 32-bit long. A single pointer of size 4 bytes is used in each block of the list to point to the next block of the list. The number of blocks required to hold the free disk block numbers is ____________. (answer in integer) Note: 1K=210 and 1G=230

(16,384) is the correct answer.

The correct answer is 16,384.
Total disk blocks: Disk size = 16 GB = 2³⁴ bytes. Block size = 2 KB = 2¹¹ bytes. Total blocks = 2³⁴ / 2¹¹ = 2²³ = 8,388,608 blocks.
Entries per list block: Each list block = 2048 bytes. Each block number = 4 bytes. One pointer (4 bytes) per list block points to the next list block. Usable entries per list block = (2048 − 4) / 4 = 2044 / 4 = 511 block numbers.
Number of list blocks needed: = ceil(2²³ / 511) = ceil(16,416.06) = 16,417 blocks.
If the pointer is assumed to not reduce usable entries (a simpler interpretation): entries per block = 2048 / 4 = 512, and blocks needed = 2²³ / 2⁹ = 2¹⁴ = 16,384.

Ques 44 GATE 2026 SET-2

A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size 4 KB. The virtual address space is 64 GB and physical address space is 1 GB. If each TLB entry stores a 4-bit process id, page number, frame number, and a 2-bit control field, then the size of the TLB (in bytes) is ___________. (answer in integer) Note: 1K=2¹⁰, 1M=2²⁰, 1G=2³⁰

(1536) is the correct answer.

The correct answer is 1536 bytes
Number of TLB entries: TLB reach = entries × page size → 2²⁰ = N × 2¹² → N = 2⁸ = 256 entries.
Page number bits: Virtual address space = 64 GB = 2³⁶ bytes. Virtual pages = 2³⁶ / 2¹² = 2²⁴. Page number = 24 bits.
Frame number bits: Physical address space = 1 GB = 2³⁰ bytes. Physical frames = 2³⁰ / 2¹² = 2¹⁸. Frame number = 18 bits.
Bits per TLB entry: 4 (process ID) + 24 (page number) + 18 (frame number) + 2 (control) = 48 bits = 6 bytes.
Total TLB size: 256 entries × 6 bytes = 1536 bytes.

Ques 45 GATE 2026 SET-2

Consider contiguous allocation of physical memory to processes using variable partitioning scheme. Suppose there are 8 holes in the memory of sizes 20 KB, 4 KB, 25 KB, 18 KB, 7 KB, 9 KB, 15 KB, and 12 KB. Assume that no two holes are adjacent. Two processes P1 of size 16 KB and P2 of size 9 KB arrive in that order, and they are allocated memory using the best-fit technique. After allocating space to P1 and P2, the number of holes of size less than 8 KB is ____________. (answer in integer) Note: 1K=2¹⁰

(3) is the correct answer.

The correct answer is 3.
Initial holes: 20, 4, 25, 18, 7, 9, 15, 12 KB.
Allocating P1 (16 KB) using best-fit: Holes large enough: 20, 25, 18 KB. Smallest sufficient = 18 KB. Remainder = 18 − 16 = 2 KB. Holes become: 20, 4, 25, 2, 7, 9, 15, 12 KB.
Allocating P2 (9 KB) using best-fit: Holes large enough: 20, 25, 9, 15, 12 KB. Smallest sufficient = 9 KB (exact fit, no remainder). The 9 KB hole is fully consumed. Holes become: 20, 4, 25, 2, 7, 15, 12 KB.
Holes with size less than 8 KB: 4, 2, 7 KB → 3 holes

Ques 46 GATE 2026 SET-2

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number 17610. The maximum possible size of the cache (in KB) for this configuration is ___________. (answer in integer) Note: 1K=2¹⁰ and 1M=2²⁰

(128) is the correct answer.

The correct answer is 128 KB
Address in binary: 0xA2C28 = 1010 0010 1100 0010 1000 (20 bits). The address is split into a Line/Index field (LO) and a Word Offset (WO).
Word Offset: The lower 6 bits (101000) represent the word offset, meaning block size = 2⁶ = 64 bytes.
Line/Index field: The remaining upper bits give the cache line address (LO) = 11 bits, meaning the number of cache lines = 2¹¹ = 2048.
Cache size: Cache address = LO + WO = 11 + 6 = 17 bits. Therefore cache size = 2¹⁷ bytes = 128 KB.

Ques 47 GATE 2026 SET-2

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ___________. (rounded off to two decimal places) Note: 1G=10⁹

(2.34) is the correct answer.

The correct answer is 2.34.
Non-pipelined time per instruction: Clock period = 1 / 1.6 GHz = 0.625 ns. Time per instruction = 5 cycles × 0.625 ns = 3.125 ns.
Pipelined CPI with hazard stalls: Ideal pipelined CPI = 1. Stall penalty per instruction = 30% × 2 stall cycles = 0.6 cycles. Effective pipelined CPI = 1 + 0.6 = 1.6 cycles.
Pipelined time per instruction: Clock period = 1 / 1.2 GHz = 0.833 ns. Time per instruction = 1.6 × 0.833 ns = 1.333 ns.
Speed-up: Speed-up = Non-pipelined time / Pipelined time = 3.125 / 1.333 = 2.34.

Ques 48 GATE 2026 SET-2

Consider a new TCP connection between a sender and a receiver. The receiver advertised window is constant at 48 KB, the maximum segment size (MSS) is 2 KB, and the slow start threshold for TCP congestion control is 16 KB. Assume that there are no timeouts or duplicate acknowledgements. The number of rounds of transmission required for the congestion control algorithm of the TCP connection to reach the congestion avoidance phase is ___________. (answer in integer) Note: 1K=2¹⁰

(4) is the correct answer.

The correct answer is 4
Given: Receiver window = 48 KB, MSS = 2 KB, ssthresh = 16 KB = 8 MSS. TCP starts with cwnd = 1 MSS = 2 KB and grows exponentially in slow start.
Round-by-round progression:
Round 1: cwnd = 1 MSS = 2 KB - Slow Start
Round 2: cwnd = 2 MSS = 4 KB - Slow Start
Round 3: cwnd = 4 MSS = 8 KB - Slow Start
Round 4: cwnd = 8 MSS = 16 KB - Slow Start ends; cwnd has reached ssthresh
Round 5: cwnd = 9 MSS = 18 KB - Congestion Avoidance begins here
The congestion avoidance phase is reached after 4 rounds of transmission. The receiver window of 48 KB is not a limiting factor since cwnd is well below it throughout.

Ques 49 GATE 2026 SET-2

Consider the digital circuit shown below with two input lines A and B, two select lines S0 and S1, and an output line Y. The blocks Q and M represent active high 2:4 decoder and 4-to-1 multiplexer, respectively. Out of 16 possible input combinations, the number of combinations that produce Y=1 is ____________. (answer in integer)
Note: One input combination is an instance of [A B S1 S0].

(5) is the correct answer.

he correct answer is 6.
The circuit consists of a 2×4 decoder (inputs A, B) feeding a 4-to-1 multiplexer M with select lines S₁ and S₀. The MUX data inputs are wired as: I₀ = AB̄, I₁ = AB̄ (or tied), I₂ = 1 (always high), I₃ = AB.
Case 1 - S₁S₀ = 10 (selects I₂ = 1): Output y = 1 regardless of A and B. Since A and B can each be 0 or 1 independently, this gives 4 combinations: (0,0,1,0), (0,1,1,0), (1,0,1,0), (1,1,1,0).
Case 2 - S₁S₀ = 00 (selects I₀ = AB̄): Output y = 1 only when AB̄ = 1, i.e., A=0, B=0. This gives 1 combination: (0,0,0,0).
Case 3 - S₁S₀ = 11 (selects I₃ = AB): Output y = 1 only when AB = 1, i.e., A=1, B=1. This gives 1 combination: (1,1,1,1).
Case 4 - S₁S₀ = 01 (selects I₁): The MUX input I₁ corresponds to the decoder output D₁ = AB̄ (which is 0 for all A,B combinations in standard 2×4 decoder with active-high outputs where only one line is high). y = 0 for all A,B. 0 combinations.
Total combinations = 4 + 1 + 1 = 6.

Ques 50 GATE 2026 SET-2

Consider the following ANSI-C program.

The output of this program is ____________. (answer in integer)
Note: Assume that the program compiles and runs successfully.

(9) is the correct answer.

Ques 51 GATE 2026 SET-2

Consider the following ANSI-C function.

The maximum possible value that can be returned from this function is ____________. (answer in integer)
Note: Ignore syntax errors (if any) in the function.

(1) is the correct answer.

The correct answer is 1.
The function computes a value based on the length = end + 1 - start of an interval, and recurses in three ways depending on length % 3. Crucially, only one branch ever adds to the return value:
length % 3 == 0: returns func(start+1, end) → length decreases by 1, new length % 3 == 2. No value added.
length % 3 == 2: returns func(start+2, end) → length decreases by 2, new length % 3 == 0. No value added.
length % 3 == 1: returns 1 + func(start, end-1) → length decreases by 1, new length % 3 == 0. +1 added here.
Why the maximum is 1: Once length % 3 == 1 fires and adds 1, the new length has remainder 0. The chain then alternates: mod 0 → mod 2 → mod 0 → mod 2 → ... until length drops below 1 and returns 0. The remainder never returns to 1 after the first firing. Therefore, no matter what valid starting values of start and end are chosen, the function can add 1 at most once throughout the entire recursive chain.
Example trace — func(0, 3), length = 4 (mod 1): 1 + func(0,2) → length=3(mod 0) → func(1,2) → length=2(mod 2) → func(3,2) → length=0 → return 0. Total = 1.
The correct maximum value that can be returned is 1.

Ques 52 GATE 2026 SET-2

The determinant of a 4×4 matrix A is 3. The value of the determinant of 2A is ____________. (answer in integer)

(48) is the correct answer.

The correct answer is 48.
For any n×n matrix A, scaling the matrix by a scalar k scales the determinant by kⁿ. This is because each row of the matrix gets multiplied by k, and there are n rows - each contributing a factor of k to the determinant.
Formula: det(kA) = kⁿ · det(A)
Here, the matrix is 4×4 (n = 4), the scalar is k = 2, and det(A) = 3. Applying the formula:
det(2A) = 2⁴ × 3 = 16 × 3 = 48.
Why kⁿ and not just k? The determinant is a multilinear function of the rows (or columns). Multiplying the entire matrix by k multiplies every one of the n rows by k, so the determinant picks up a factor of k exactly n times - giving kⁿ, not k.
A common mistake is to compute 2 × 3 = 6 (forgetting the matrix dimension) or 2³ × 3 = 24 (using n−1). Always use the full dimension n in the formula.

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