CS and IT Gate 2026 Set-1 Questions with Answer

Option A — False.
Either the client or the server can initiate the closing of a TCP connection. TCP uses a 4-way handshake (FIN, ACK, FIN, ACK) for connection termination and either side is free to send the first FIN. It is not restricted to the client only.
Option B - True.
TCP supports simultaneous close. Both the client and server can send a FIN segment at the same time without waiting for the other side to initiate first. This is a valid and well-defined scenario in TCP's connection termination process.
Option C - False.
TCP uses a 3-way handshake (SYN, SYN-ACK, ACK) before data transfer begins — not a 2-way handshake. A 2-way handshake is insufficient for TCP as it cannot confirm that both sides are ready to communicate reliably.
Option D - False.
TCP is a full duplex protocol. Data can be sent and received simultaneously in both directions over the same connection. Half duplex would mean only one side can transmit at a time.
The correct statement is B - The client and server can initiate closing of the connection at the same time (Option B)

The correct answer is Option A: 21 frames.
To achieve 100% link utilization, the sender must keep transmitting without ever going idle while waiting for an acknowledgement.
Transmission time of one frame:
T_t = Frame size / Bandwidth = 1000 bits / 100,000 bps = 10 ms
Round Trip Time (RTT):
RTT = 2 × Propagation delay = 2 × 100 ms = 200 ms
(ACK transmission time = 0, processing time = 0)
Minimum window size for 100% utilization:
W = (T_t + RTT) / T_t = (10 + 200) / 10 = 210 / 10 = 21 frames
With W = 21, the sender continuously transmits 21 frames in the time it takes for the first ACK to arrive back, keeping the link fully busy at all times.

To find the average time to read a random sector, we must calculate the total disk access time. This consists of three main components: Average Seek Time, Average Rotational Latency, and Transfer Time.

1. Average Seek Time
This is the time it takes for the read/write head to move to the correct track. The problem directly provides the average seek time. (Note: The adjacent track time of 2 ms is a distractor for a random sector calculation).
Average Seek Time = 5 ms.

2. Average Rotational Latency
This is the time it takes for the target sector to rotate under the read/write head. On average, this takes half of a full rotation.
First, find the time for one full rotation:
Rotational speed = 15000 revolutions per minute (rpm).
Revolutions per second = 15000 / 60 = 250 rps.
Time for 1 full rotation = 1 / 250 seconds = 0.004 seconds = 4 ms.
Average Rotational Latency = Half of a full rotation = 4 ms / 2 = 2 ms.

3. Transfer Time
This is the time it takes to actually read the data from the sector as it passes under the head.
Since one full rotation (4 ms) reads an entire track consisting of 400 sectors:
Transfer Time for 1 sector = 4 ms / 400 = 0.01 ms.

4. Total Average Access Time
Total Time = Average Seek Time + Average Rotational Latency + Transfer Time
Total Time = 5 ms + 2 ms + 0.01 ms = 7.01 ms.

The question asks for the answer as an integer in milliseconds. Rounding 7.01 gives us exactly 7.

Correct Answer: 7

To find the total number of stall cycles caused by structural hazards in the EX stage, we need to determine how many clock cycles each instruction spends occupying that stage.
1. Understanding Stall Cycles
The pipeline clock cycle duration is 1 nanosecond (ns). Because execution must happen in discrete clock cycles, if an instruction''s execution time (t_EX) is not an exact integer, it will occupy the EX stage for the ceiling of its t_EX (i.e., ceil(t_EX) cycles).
In an ideal pipeline, an instruction leaves the stage after exactly 1 cycle to let the next instruction enter. If an instruction stays for C cycles, it blocks the pipeline, causing C - 1 stall cycles.
2. Calculating Stalls per Instruction Type
Using the formula Stalls = ceil(t_EX) - 1, let''s look at each instruction type:
- LOAD: t_EX = 1.8 ns → ceil(1.8) = 2 cycles. Stalls = 2 - 1 = 1
- IMUL: t_EX = 1.5 ns → ceil(1.5) = 2 cycles. Stalls = 2 - 1 = 1
- IDIV: t_EX = 2.5 ns → ceil(2.5) = 3 cycles. Stalls = 3 - 1 = 2
- FADD: t_EX = 1.7 ns → ceil(1.7) = 2 cycles. Stalls = 2 - 1 = 1
- FSUB: t_EX = 1.7 ns → ceil(1.7) = 2 cycles. Stalls = 2 - 1 = 1
- FMUL: t_EX = 2.8 ns → ceil(2.8) = 3 cycles. Stalls = 3 - 1 = 2
- FDIV: t_EX = 3.2 ns → ceil(3.2) = 4 cycles. Stalls = 4 - 1 = 3
- Other: t_EX < 1.0 ns → ceil(<1.0) = 1 cycle. Stalls = 1 - 1 = 0
3. Total Stall Cycles for Program P
Now we multiply the stall cycles per instruction by its frequency (M) in the sequence of 100 instructions:
- LOAD: 15 × 1 = 15 stalls
- IMUL: 10 × 1 = 10 stalls
- IDIV: 5 × 2 = 10 stalls
- FADD: 10 × 1 = 10 stalls
- FSUB: 5 × 1 = 5 stalls
- FMUL: 15 × 2 = 30 stalls
- FDIV: 5 × 3 = 15 stalls
- Other: 35 × 0 = 0 stalls
Total Stalls = 15 + 10 + 10 + 10 + 5 + 30 + 15 + 0 = 95.
Correct Answer: 95

Analysing each addressing mode:
P. Immediate → 4. Constant
In immediate addressing, the operand is directly embedded in the instruction itself. This is used to represent a constant value. Example: MOV R1, #5 (5 is a constant).
Q. Indirect → 2. Pointer
In indirect addressing, the address field contains a pointer — the address of a memory location that holds the actual address of the operand. This is exactly how pointers work.
R. Base with index → 1. Element of an array
Base register holds the starting address of an array and the index register holds the offset for each element. This is the classic way to access array elements. Example: Base + Index = address of arr[i].
S. Base with offset → 3. Element of a record
Base register holds the starting address of a record (struct) and a fixed offset is used to access a specific field within it. This is how struct members are accessed in memory.
The correct match is P-4, Q-2, R-1, S-3 (Option B)

The correct answer is Option A.
In a load-store architecture, arithmetic and logic instructions can only operate on register operands — they cannot directly access memory. Memory is accessed exclusively through Load (memory → register) and Store (register → memory) instructions. This is the fundamental characteristic of RISC-style processors.
To compute z = x + y where x, y, z are memory operands, the correct sequence is:
Load R0, x - bring x from memory into register R0
Load R1, y - bring y from memory into register R1
ADD R2, R0, R1 - add R0 and R1, store result in R2 (first operand R2 is the destination)
Store Z, R2 - write result from R2 back to memory location z
This is exactly Option A and it correctly follows all load-store rules.
Option B - ADD Z, R0, y: uses memory operand y directly in ADD. Not allowed in load-store ISA.
Option C - ADD R0, x, y: uses two memory operands in ADD. Not allowed.
Option D - ADD Z, x, y: uses memory as both operands and destination in ADD. Not allowed.
The rule is simple - in load-store ISA, ADD never touches memory. Load and Store are the only instructions that do.

The correct answer is Option C: Read-after-write.
Among all register dependencies, RAW is the one that causes a true data hazard in a pipelined processor. It happens when a later instruction needs to read a register that an earlier instruction is still in the process of writing. Since the pipeline overlaps instruction execution, the later instruction may read a stale (old) value before the write is completed - this is a genuine hazard.
Here"s a quick summary of all four dependencies:
• RAW (Read after Write): True data dependency - causes real hazards. The pipeline must stall or use data forwarding to resolve it.
• WAR (Write after Read): Anti-dependency - not a hazard in a simple in-order pipeline since the read always happens before the write in program order.
• WAW (Write after Write): Output dependency - not a hazard in a basic in-order pipeline; writes complete in program order.
• RAR (Read after Read): Not a dependency at all - reading a register from multiple instructions simultaneously causes no conflict whatsoever.

Step 1 — Decode X = 35C00000:
In binary: 0 01101011 10000000000000000000000
Exponent = 107 − 127 = −20. Mantissa = 1.1₂ = 1.5
X = 1.5 × 2⁻²⁰ = 1.10000 × 2⁻²⁰
Step 2 — Decode Y = 34A00000:
In binary: 0 01101001 01000000000000000000000
Exponent = 105 − 127 = −22. Mantissa = 1.01₂ = 1.25
Y = 1.25 × 2⁻²² = 1.010 × 2⁻²²
Step 3 — Align exponents:
Shift Y right by 2 to match X''s exponent −20:
Y = 0.01010 × 2⁻²⁰
Step 4 — Add mantissas:
1.10000 × 2⁻²⁰
0.01010 × 2⁻²⁰
= 1.11010 × 2⁻²⁰
Step 5 — Encode Z:
Sign = 0, Exponent = −20 + 127 = 107 = 01101011₂
Mantissa field = 1101 0000 0000 0000 0000 000
Full bits: 0 01101011 11010000000000000000000
= 0011 0101 1110 1000 0000 0000 0000 0000
= 35E80000
Correct answer: C — 35E80000.

Physical address is 32 bits. Block size = 128 = 2⁷ bytes → 7 offset bits. Cache capacity = 2²³ bytes → total cache lines = 2²³/2⁷ = 2¹⁶.
Direct Mapped Cache — TAG bits M
In a direct mapped cache every cache line maps to exactly one set, so number of sets = number of lines = 2¹⁶. Index bits = 16. TAG bits M = 32 − 16 − 7 = 9.
K-way Set Associative Cache — TAG bits N
With K = 2^L ways, each set holds K lines. Number of sets = 2¹⁶ / 2^L = 2^16−L. Set index bits = 16 − L. TAG bits N = 32 − (16−L) − 7 = 9 + L = M + L.
The intuition is clear — going from direct mapped to K-way set associative reduces the number of sets by a factor of K = 2^L, so the index field shrinks by L bits. Those L bits move into the TAG field, making the TAG L bits longer. Hence N = M + L.
Correct answer: A — N = M + L ✓

To find the position of the element 60 in the postorder traversal, we first need to reconstruct the Binary Search Tree (BST) using the given preorder sequence.
1. Understanding the Properties
- Preorder Traversal: Visits nodes in the order: Root, Left Subtree, Right Subtree.
- BST Property: All elements in the left subtree are strictly smaller than the root, and all elements in the right subtree are strictly greater than the root.
2. Reconstructing the Tree
Given Preorder: 50, 25, 13, 10, 30, 60, 55, 70, 65, 80, 75, 90
- The first element, 50, is the Root.
- Elements smaller than 50 form the left subtree: {25, 13, 10, 30}
- Elements greater than 50 form the right subtree: {60, 55, 70, 65, 80, 75, 90}
Building the Left Subtree (Root = 25):
Left of 25: {13, 10} → Root is 13, Left is 10.
Right of 25: {30}
Building the Right Subtree (Root = 60):
Left of 60: {55}
Right of 60: {70, 65, 80, 75, 90} → Root is 70. Left is 65. Right is {80, 75, 90} (Root 80, Left 75, Right 90).
3. Finding the Postorder Traversal
Postorder visits nodes in the order: Left Subtree, Right Subtree, Root.
- Left Subtree of 50: 10, 13, 30, 25
- Right Subtree of 50: 55, 65, 75, 90, 80, 70, 60
- Root: 50

Full Postorder Sequence: 10, 13, 30, 25, 55, 65, 75, 90, 80, 70, 60, 50
4. Determining the Position
Counting the elements starting from position 1:
1: 10, 2: 13, 3: 30, 4: 25, 5: 55, 6: 65, 7: 75, 8: 90, 9: 80, 10: 70, 11: 60
The element 60 is at the 11th position.
Correct Answer: 11

In a binary heap stored in a 1-indexed array of n elements, node at index i is a leaf if and only if its left child index 2i exceeds n, i.e., i > n/2. Since n is odd, ⌊n/2⌋ = (n−1)/2. So all leaves are at indices from (n+1)/2 to n, and all internal nodes (non-leaves) are at indices 1 to (n−1)/2.
Option A — (n+1)/2 — IS a leaf
Since n is odd, (n+1)/2 is a whole number. This is exactly the first leaf node in the heap. Its left child would be at index n+1 which exceeds n, confirming it is a leaf. A is not the answer.
Option B — (n−1)/2 — NOT a leaf (internal node)
(n−1)/2 is strictly less than (n+1)/2, so it falls in the internal node range. Its left child is at index 2 × (n−1)/2 = n−1 ≤ n, meaning it has at least one child. So it is an internal node, not a leaf. B is correct.
Option C — (n−3)/2 — NOT a leaf (internal node)
(n−3)/2 = (n−1)/2 − 1, which is even further into the internal node region. Its left child is at n−3+2 = n−1 ≤ n, confirming it has children. C is also an internal node and correct.
Option D — n — IS a leaf
The last element n always has no children since its left child would be at 2n which is far beyond the array. It is definitely a leaf. D is not the answer.
Correct answer: B and C ✓

Hash function h(x) = (x+7) mod 11. Linear probing on collision. Tracing each insertion:
Insert 1: h(1) = 8 mod 11 = 8. Position 8 is empty → placed at 8.
Insert 13: h(13) = 20 mod 11 = 9. Position 9 is empty → placed at 9.
Insert 22: h(22) = 29 mod 11 = 7. Position 7 is empty → placed at 7.
Insert 15: h(15) = 22 mod 11 = 0. Position 0 is empty → placed at 0.
Insert 11: h(11) = 18 mod 11 = 7. Position 7 is occupied (22). Probe 8 — occupied (1). Probe 9 — occupied (13). Probe 10 — empty → placed at 10.
Insert 24: h(24) = 31 mod 11 = 9. Position 9 is occupied (13). Probe 10 — occupied (11). Probe 0 — occupied (15). Probe 1 — empty → placed at 1.
Final state: positions 0(15), 1(24), 7(22), 8(1), 9(13), 10(11) are occupied. Positions 2, 3, 4, 5, 6 are empty. Among the options, position 2 is empty while positions 0, 1 and 10 are all occupied.
Correct answer: C — Position 2 is empty.

A full binary tree requires every node to have exactly 0 or 2 children. With 23 nodes, the number of internal nodes = (23−1)/2 = 11 and the number of leaves = (23+1)/2 = 12.
To maximise the height, we build the tree as a right-leaning skewed chain. At each level along the main path, we place one internal node whose one child is a leaf (terminating there) and whose other child continues the chain down to the next level. This uses one internal node and one leaf per level.
With 11 internal nodes, the main chain goes from level 0 to level 10, consuming 10 internal nodes and 10 leaves (one leaf per level as a sibling branch). The 11^th internal node sits at level 10 — it has no more internal node children available, so both of its children must be leaves at level 11. This accounts for the remaining 2 leaves, giving a total of 12 leaves ✓
The deepest leaf is at level 11, and since height is defined as the number of edges in the longest root-to-leaf path, the maximum height = 11.
Correct answer: 11 ✓