CS/IT Gate Yearwise
CS/IT Gate 2025 (Set 2)
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CS/IT Gate 2021 (Set 1)
CS/IT Gate 2021 (Set 2)
CS/IT Gate 2020
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CS/IT Gate 2017 (Set 1)
CS/IT Gate 2017 (Set 2)
CS/IT Gate 2016 (Set 1)
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CS/IT Gate 2015 (Set 1)
CS/IT Gate 2015 (Set 2)
CS/IT Gate 2015 (Set 3)
CS/IT Gate 2014 (Set 1)
CS/IT Gate 2014 (Set 2)
CS/IT Gate 2014 (Set 3)
CS and IT GATE 2025 SET-2 Questions with Answer
Ques 14 Computer Networks
Consider a network that uses Ethernet and IPv4. Assume that IPv4 headers do not use any options field. Each Ethernet frame can carry a maximum of 1500 bytes in its data field. A UDP segment is transmitted. The payload (data) in the UDP segment is 7488 bytes.
Which ONE of the following choices has the CORRECT total number of fragments transmitted and the size of the last fragment including IPv4 header?
Ques 15 Computer Networks
Suppose we are transmitting frames between two nodes using Stop-and-Wait protocol. The frame size is 3000 bits. The transmission rate of the channel is 2000 bps (bits/second) and the propagation delay between the two nodes is 100 milliseconds. Assume that the processing times at the source and destination are negligible. Also, assume that the size of the acknowledgement packet is negligible. Which ONE of the following most accurately gives the channel utilization for the above scenario in percentage?
Ques 16 Computer Organization and Architecture
Which of the following is/are part of an Instruction Set Architecture of a processor?
Ques 17 Computer Organization and Architecture
The following two signed 2's complement numbers (multiplicand M and multiplier Q) are being multiplied using Booth's algorithm:
M: 1100 1101 1110 1101 and Q: 1010 0100 1010 1010
The total number of addition and subtraction operations to be performed is ______ (Answer in integer)
Ques 18 Computer Organization and Architecture
For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block.
Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?
Ques 19 Computer Organization and Architecture
Three floating point numbers X, Y, and Z are stored in three registers RX, Ry, and Rz, respectively in IEEE 754 single precision format as given below in hexadecimal:
RX=0xC1100000, RY=0x40C00000, and RZ=0x41400000
Which of the following option(s) is/are CORRECT?
Ques 20 Computer Organization and Architecture
Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the "hit rate" for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the "hit rate" is 80% and the "miss penalty" for transferring data from L2 cache to L1 cache is 10 ns. The "miss penalty" for the data to be transferred from main memory to L2 cache is 100 ns.
Then the average memory access time in this system in nanoseconds is ______ (rounded off to one decimal place)
Ques 21 Computer Organization and Architecture
A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is ______ (rounded off to two decimal places)
Ques 22 Computer Organization and Architecture
An application executes 6.4×108 number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is ______ (rounded off to one decimal place)
Instruction type | Clock cycles required per instruction (CPI) | Number of instructions executed |
Branch | 2 | 2.25×108 |
Load | 5 | 1.20×108 |
Store | 4 | 1.65×108 |
Arithmetic | 3 | 1.30×108 |
Ques 23 Data Structures
Consider a binary tree T in which every node has either zero or two children. Let n>0 be the number of nodes in T.
Which ONE of the following is the number of nodes in T that have exactly two children?
Ques 24 Data Structures
Suppose the values 10, -4, 15, 30, 20, 5, 60, 19 are inserted in that order into an initially empty binary search tree. Let T be the resulting binary search tree. The number of edges in the path from the node containing 19 to the root node of T is ______ (Answer in integer)
Ques 25 Data Structures
Consider a stack data structure into which we can PUSH and POP records. Assume that each record pushed in the stack has a positive integer key and that all keys are distinct.
We wish to augment the stack data structure with an O(1) time MIN operation that returns a pointer to the record with smallest key present in the stack
1) without deleting the corresponding record, and
2) without increasing the complexities of the standard stack operations.
Which one or more of the following approach(es) can achieve it?
Ques 26 Databases
An audit of a banking transactions system has found that on an earlier occasion, two joint holders of account A attempted simultaneous transfers of Rs. 10000 each from account A to account B. Both transactions read the same value, Rs. 11000, as the initial balance in A and were allowed to go through. B was credited Rs. 10000 twice. A was debited only once and ended up with a balance of Rs. 1000.
Which of the following properties is/are certain to have been violated by the system?

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