CS and IT GATE 2024 SET-2 Questions with Answer

Ques 40 Computer Science

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A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is __________.

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Ques 41 Computer Science

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A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ___________.

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Ques 42 Computer Science

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Let L₁ be the language represented by the regular expression b*ab*(ab*ab*)* and L₂ = {w ∈ (a + b)* | |w| ≤ 4}, where |w| denotes the length of string w. The number of strings in L₂ which are also in L₁ is ___________.

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Ques 43 Computer Science

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Let Z_n be the group of integers {0,1,2,...,n-1} with addition modulo n as the group operation. The number of elements in the group Z₂ x Z₃ x Z₄ that are their own inverses is

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Ques 44 Computer Science

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Consider a 32-bit system with 4 KB page size and page table entries of size 4 bytes each. Assume 1 KB = 2¹⁰ bytes. The OS uses a 2-level page table for memory management, with the page table containing an outer page directory and an inner page table. The OS allocates a page for the outer page directory upon process creation. The OS uses demand paging when allocating memory for the inner page table, i.e., a page of the inner page table is allocated only if it contains at least one valid page table entry.
An active process in this system accesses 2000 unique pages during its execution, and none of the pages are swapped out to disk. After it completes the page accesses, let X denote the minimum and Y denote the maximum number of pages across the two levels of the page table of the process. The value of X + Y is ________.

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Ques 45 Computer Science

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Consider the following augmented grammar, which is to be parsed with a SLR parser. The set of terminals is {a,b,c,d,#,&}.
S' → S
S → SS | Aa | bAc | Bc | bBa
𝐴 → 𝑑#
𝐵 → @
Let I₀ = CLOSURE({S' → •S}) The number of items in the set GOTO(I₀, S) is

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Ques 46 Data Structure

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Let S1 and S2 be two stacks. S1 has capacity of 4 elements. S2 has capacity of 2 elements. S1 already has 4 elements: 100, 200, 300, and 400, whereas S2 is empty, as shown below.

Only the following three operations are available:
PushToS2: Pop the top element from S1 and push it on S2.
PushToS1: Pop the top element from S2 and push it on S1.
GenerateOutput: Pop the top element from S1 and output it to the user.
Note that the pop operation is not allowed on an empty stack and the push operation is not allowed on a full stack.
Which of the following output sequences can be generated by using the above operations?

A

100, 200, 400, 300

B

200, 300, 400, 100

C

400, 200, 100, 300

D

300, 200, 400, 100

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Ques 47 Design Algorithm Analysis

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The chromatic number of a graph is the minimum number of colours used in a proper colouring of the graph. The chromatic number of the following graph is _________

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Ques 48 Design Algorithm Analysis

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The number of distinct minimum-weight spanning trees of the following graph is _________

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Ques 49 Digital Logic Design

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A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.
R-type Instruction Format:

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.
Let 𝑋 be the number of bits used to encode the UNUSED field, 𝑌 be the number of bits used to encode the OPCODE field, and 𝑍 be the number of bits used to encode the immediate value/address field. The value of 𝑋 + 2𝑌 + 𝑍 is ________

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Ques 50 Digital Logic Design

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Consider 4-variable functions f1, f2, f3, f4 expressed in sum-of-minterms form as given below.
f1 = ∑(0,2,3,5,7,8,11,13)
f2 = ∑(1,3,5,7,11,13,15)
f3 = ∑(0,1,4,11)
f4 = ∑(0,2,6,13)

With respect to the circuit given above, which of the following options is/are CORRECT?

A

Y =∑(0,1,2,11,13)

B

Y =Π(3,4,5,6,7,8,9,10,12,14,15)

C

Y =∑(0,1,2,3,4,5,6,7)

D

Y =Π(8,9,10,11,12,13,14,15)

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Ques 51 Digital Logic Design

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Consider the following expression: 𝑥[𝑖]=(𝑝+𝑟)∗−𝑠[𝑖]+𝑢/𝑤. The following sequence shows the list of triples representing the given expression, with entries missing for triples (1), (3), and (6).

Which one of the following options fills in the missing entries CORRECTLY?

A

(1) =[]⁡⁡𝑠⁡⁡𝑖   (3) * (0) (2)   (6) []=⁡⁡𝑥⁡⁡𝑖

B

(1) []=⁡⁡𝑠⁡⁡𝑖   (3) –⁡(0)⁡(2)   (6) =[] ⁡𝑥⁡⁡(5)

C

(1) =[] ⁡𝑠⁡𝑖   (3) * (0)⁡⁡(2)   (6) []= ⁡𝑥⁡⁡(5)

D

(1) []= ⁡𝑠⁡⁡𝑖   (3) –⁡(0)⁡(2)   (6) =[] 𝑥⁡⁡𝑖

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Ques 52 Digital Logic Design

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Consider an array X that contains n positive integers. A subarray of X is defined to be a sequence of array locations with consecutive indices. The C code snippet given below has been written to compute the length of the longest subarray of X that contains at most two distinct integers. The code has two missing expressions labelled (𝑃)⁡and (𝑄).

Which one of the following options gives the CORRECT missing expressions?
(Hint: At the end of the i-th iteration, the value of len1 is the length of the longest subarray ending with X[i] that contains all equal values, and len2 is the length of the longest subarray ending with X[i] that contains at most two distinct values.)

A

𝑃) len1+1     (𝑃) 1

B

(𝑃) 1             (𝑃) len2+1

C

(𝑄) len2+1   (𝑄) len1+1

D

(𝑄) len2+1   (𝑄) len1+1

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