CS and IT GATE 2020 Questions with Answer

Ques 14 C Programming

Consider the following C functions.

int tob (int b, int* arr) {
int i;
for (i = 0; b>0; i++) {
if (b%2)
arr [i] = 1;
else
arr[i] = 0;
b = b/2;
}
return (i);
}

int pp(int a, int b) {
int arr[20];
int i, tot = 1, ex, len;
ex = a;
len = tob(b, arr);
for (i=0; i if (arr[i] ==1)
tot = tot * ex;
ex= ex*ex;
}
return (tot) ;
}

The value returned by pp(3,4) is ________ .

81 is the correct answer.

Ques 15 C Programming

Consider the following C functions.

int fun1(int n)
{
static int i= 0;
if (n > 0) {
++i;
fun1(n-1);
}
return (i);
}

int fun2(int n) {
static int i= 0;
if (n>0) {
i = i+ fun1 (n) ;
fun2(n-1) ;
}
return (i);
}

The return value of fun2(5) is ________ .

55 is the correct answer.

Ques 16 C Programming

Consider the following C program.
#include <stdio.h>
int main () {
int a[4][5] = {{1, 2, 3, 4, 5},
{6, 7, 8, 9, 10},
{11, 12, 13, 14, 15},
{16, 17, 18, 19, 20}};
printf("%dn", *(*(a+**a+2)+3));
return(0);
}

The output of the program is _______

19 is the correct answer.

Ques 17 COA

An organization requires a range of IP address to assign one to each of its 1500 computers. The organization has approached an Internet Service Provider (ISP) for this task. The ISP uses CIDR and serves the requests from the available IP address space 202.61.0.0/17. The ISP wants to assign an address space to the organization which will minimize the number of routing entries in the ISP’s router using route aggregation. Which of the following address spaces are potential candidates from which the ISP can allot any one of the organization ?

I. 202.61.84.0 / 21
II. 202.61.104.0 / 21
III. 202.61.64.0 / 21
IV. 202.61.144.0 / 21

I and II only

II and III only

III and IV only

I and IV only

Ques 18 COA

A computer system with a word length of 32 bits has a 16 MB byte- addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.

A1 = 0x42C8A4
A2 = 0x546888
A3 = 0x6A289C
A4 = 0x5E4880

Which one of the following is TRUE ?

A1 and A4 are mapped to different cache sets.

A2 and A3 are mapped to the same cache set.

A3 and A4 are mapped to the same cache set.

A1 and A3 are mapped to the same cache set.

Ques 19 COA

Consider three registers R1, R2, and R3 that store numbers in IEEE−754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.

If R3 = ^R1/ _R2, what is the value stored in R3 ?

0x40800000

0xC0800000

0x83400000

0xC8500000

Ques 20 COA

Consider the following statements.
I. Daisy chaining is used to assign priorities in attending interrupts.
II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.
III. In polling,the CPU periodically checks the status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Ⅰ and Ⅱ only

Ⅰ and Ⅳ onlyⅠ and Ⅲ onlya

Ⅰ and Ⅲ only

Ⅲ only

Ques 21 COA

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______ .

14 is the correct answer.

Ques 22 COA

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5- stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is __________ .

2.16 is the correct answer.

Ques 23 COA

A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is ________ .

13.5 is the correct answer.

Ques 24 COA

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is _________

5 is the correct answer.

Ques 25 Compiler Design

Consider the productions A → PQ and A → XY. Each of the five non-terminals A,P,Q,X, and Y has two attributes: s is a synthesized attribute, and i is an inherited attribute. Consider the following rules.

Rule 1: P.i=A.i+2, Q.i=P.i+A.i, and A.s=P.s+Q.s
Rule 2: X.i=A.i+Y.s and Y.i=X.s+A.i

Which one of the following is TRUE ?

Both Rule 1 and Rule 2 are L-attributed

Only Rule 1 is L-attributed

Only Rule 2 is L-attributed

Neither Rule 1 nor Rule 2 is L-attributed

Ques 26 Compiler Design

Consider the following statements.
I. Symbol table is accessed only during lexical analysis and syntax analysis.
II. Compilers for programming languages that support recursion necessarily need heap storage for memory allocation in the run-time environment.
III. Errors violating the condition ‘any variable must be declared before its use’ are detected during syntax analysis.
Which of the above statements is/are TRUE ?

I only

I and III only

Ⅱ only

None of Ⅰ, Ⅱ and Ⅲ

1 2 3 4 5

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CS and IT GATE 2020 Questions with Answer