Electrical Engineering > GATE 2025 > Fault Analysis
The bus impedance matrix of a 3-bus system (in pu) is
A symmetrical fault (through a fault impedance of j0.007 pu) occurs at bus 2.
Neglecting pre-fault loading conditions, the voltage at bus 1, during the fault is ______ pu (round off to three decimal places).

Neglecting pre-fault loading conditions, the voltage at bus 1, during the fault is ______ pu (round off to three decimal places).
Correct : 0.395
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