Electrical Engineering > GATE 2018 > Flip-Flops
Which one of the following statements is true about the digital circuit shown in the figure
A
It can be used for dividing the input frequency by 3.
B
It can be used for dividing the input frequency by 5.
C
It can be used for dividing the input frequency by 7.
D
It cannot be reliably used as a frequency divider due to disjoint internal cycles.

Correct : b

Similar Questions

The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is '0', then the fr...
#944 MCQ
The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is '0', then the fr...
#944 MCQ
The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is '0', then the fr...
#944 MCQ

Related Topics

No tags found

Unique Visitor Count

Total Unique Visitors

Loading......