EC > GATE 2025 > Sequential Circuits
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns.
The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is
The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is
Correct : 200
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