EC > GATE 2025 > Sequential Circuits
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input PO is set to logic '0' and P1 is set to logic '1' at all times. The timing diagram of the inputs SEL and S are also shown below.
The sequence of output Y from time T0 to T3 is
The sequence of output Y from time T0 to T3 is
Correct : a
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