EC > GATE 2024 > Sequential Circuits
The sequence of states $(Q_1 Q_0)$ of the given synchronous sequential circuit is
A
$00 → 10 → 11 → 00$
B
$11 → 00 → 10 → 01 → 00$
C
$01 → 10 → 11 → 00 → 01$
D
$00 → 01 → 10 → 00$

Correct : D

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sequential circuit EC GATE 2024 synchronous sequential circuit circuit state sequence GATE EC 2024 circuit state transitions EC gate 2024 sequential circuit states circuit state changes

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