Correct : 3

The answer to this question is 3 ns.
To understand why, let"s first recall what "critical path delay" means in a digital circuit. It is simply the longest delay path from any input to any output - the path that takes the most time for a signal to travel through, and it is this path that limits how fast the whole circuit can operate.
In this circuit, multiple NAND gates are connected together, and each one has a propagation delay of 1 ns. Now, not every input-to-output path goes through the same number of gates. Some signals might pass through just one or two gates, while others have to travel through more. The critical path is the one where the signal has to pass through the maximum number of gates.
Looking at the given circuit carefully, the longest path from input to output passes through 3 NAND gates in series. Since each gate contributes a delay of 1 ns, the total critical path delay is:
Critical Path Delay = 3 × 1 ns = 3 ns
The other paths in the circuit are shorter - they pass through fewer gates - so their delays are less than 3 ns. Only the longest chain matters when determining the critical path, and here that longest chain has exactly 3 gates.