EC > GATE 2022 > Sequential Circuits
For the circuit shown, the clock frequency is f0 and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, _______.
A
frequency is f0/4 and duty cycle is 50%
B
frequency is f0/4 and duty cycle is 25%
C
frequency is f0/2 and duty cycle is 50%
D
frequency is f0 and duty cycle is 25%

Correct : a

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