MOSFET Sample & Hold Circuit | GATE EC 2020 Question 46

```

EC > GATE 2020 > MOSFET Circuits

An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to -10 V. If the input voltage V_I lies between ±10 V, the minimum and the maximum values of VG required for proper sampling and holding respectively, are

A

3 V and -3 V.

B

10 V and -10 V.

C

13 V and -7 V.

D

10 V and -13 V.

Correct : c

Similar Questions

In the circuit shown below, VI and V2 are bias voltages. Based on input and output impedances, the circuit behaves as a

#106 MCQ

In the circuit below, the voltage VL is ____ V (rounded off to two decimal places).

#149 Fill in the Blanks

The identical MOSFETS M1 and M2 in the circuit given below are ideal and biased in the saturation region. M1 and M2 have a transconductance gm of 5 ms.The input...

#199 MCQ

Related Topics

MOSFET threshold voltage GATE EC 2020 sample and hold circuit VG threshold voltage MOSFET biasing EC GATE EC 2020 questions MOSFET circuit analysis sample hold circuit EC

Unique Visitor Count

Total Unique Visitors

Loading......