EC > GATE 2019 > Digital Electronics
A standard CMOS inverter is designed with equal rise and fall times (βn=βp). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NML) and the HIGH noise margin NMH?
A
NML increases and NMH decreases.
B
NML decreases and NMH increases.
C
Both NML and NMH increase.
D
No change in the noise margins.

Correct : a

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