Figure I shows a 4-bit ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder are initially reset to 0. At t=0 the inputs to the 4-bit adder are changed to X₃X₂X₁X₀=1100, Y₃Y₂Y₁Y₀=0100 and Z₀=1. The output of the ripple carry adder will be stable at t(in ns)=