EC > GATE 2017 SET-1 > Sequential Circuits
A 4-bit shift register circuit configured for right-shift operation. i.e. Din→A, A→B, B→C, C→D. is shown. If the present state of the shift register is ABCD=1101 the number of clock cycles required to reach the state ABCD=1111 is
Correct : 10
Similar Questions
The sequence of states $(Q_1 Q_0)$ of the given synchronous sequential circuit is
The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are
In a given sequential circuit, initial states are Q1 = 1 and Q2 = 0. For a clock frequency of 1 MHz, the frequency of signal Q2 in kHz, is ____ (rounded off to...
Total Unique Visitors
Loading......