EC > GATE 2015 SET-2 > Digital Circuits
A 1-to-8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB) and Y0 to Y7 as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input E and address inputs A0 and A1) as shown in the figure. Din, S0, S1 and S2 are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be
Correct : d
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