Computer Sciences > GATE 2026 SET-2 > Computer Organization
A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an
average of 5 clock cycles to complete the execution of an instruction. To improve
the performance, the system was pipelined with a goal of achieving an average
throughput of one instruction per clock cycle. However, it could operate only at
1.2 GHz due to pipeline overheads. While executing a program in the pipelined
design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards.
The speed-up obtained by the pipelined design over the non-pipelined one for this
program is ___________. (rounded off to two decimal places)
Note: 1G=109
Correct : 2.34
The correct answer is 2.34.
Non-pipelined time per instruction: Clock period = 1 / 1.6 GHz = 0.625 ns. Time per instruction = 5 cycles × 0.625 ns = 3.125 ns.
Pipelined CPI with hazard stalls: Ideal pipelined CPI = 1. Stall penalty per instruction = 30% × 2 stall cycles = 0.6 cycles. Effective pipelined CPI = 1 + 0.6 = 1.6 cycles.
Pipelined time per instruction: Clock period = 1 / 1.2 GHz = 0.833 ns. Time per instruction = 1.6 × 0.833 ns = 1.333 ns.
Speed-up: Speed-up = Non-pipelined time / Pipelined time = 3.125 / 1.333 = 2.34.
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