Computer Sciences > GATE 2026 SET-1 > Sequential Circuits
Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1. The Next State table of the counter is as shown below. The counter is built as a synchronous sequential circuit using D flip-flops.
Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, D1 and D0?
A
D1 = PQ1 + P̄Q0 + Q10    D0 = PQ0 + P̄Q1 + Q10
B
D1 = P̄Q1 + P̄Q0 + Q1Q0    D0 = P̄Q̄0 + P̄Q1 + Q10
C
D1 = P̄Q1 + P̄Q0 + Q1Q0    D0 = P̄Q0 + P̄Q1 + Q10
D
D1 = PQ̄1 + P̄Q0 + Q1Q0    D0 = PQ̄0 + P̄Q1 + Q10

Correct : b

For D flip-flops, D1 = Q1+ and D0 = Q0+ directly from the next state table. Reading the next state values from the table and deriving the Boolean expressions using Karnaugh maps:
D1 = P̄Q1 + P̄Q0 + Q1Q0
P̄Q0 covers the cases where P=0 and Q0=1 (states 01 and 11 with P=0). P̄Q1 covers P=0 and Q1=1 (states 10 and 11 with P=0). Q1Q0 covers the single remaining case where P=1, Q1=1, Q0=1 (state 11 with P=1, which must go to 1). All eight rows verify correctly against the state table.
D0 = P̄Q̄0 + P̄Q1 + Q1Q̄0
P̄Q̄0 covers P=0 and Q0=0 (states 00 and 10 with P=0). P̄Q1 covers P=0 and Q1=1 (states 10 and 11 with P=0). Q1Q̄0 covers Q1=1 and Q0=0 (state 10 with P=1). All eight rows verify correctly against the state table.
Correct answer: B

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saturating counter D flip-flop GATE 2026 GATE CS 2026 Set-1 Q43 2-bit saturating up down counter GATE D1 D0 expressions sequential circuit GATE synchronous counter D flip-flop GATE digital logic GATE 2026 next state table D flip-flop input equations GATE

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