Computer Sciences > GATE 2025 SET-2 > Pipelining
A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is ______ (rounded off to two decimal places)

Correct : 261.04 µs

In a pipeline, the clock cycle is governed by the slowest stage. The stage delays are 180, 250, 150, 170, and 250 ns. The maximum among these is 250 ns. Adding the inter-stage latch delay of 10 ns gives us the clock cycle time = 250 + 10 = 260 ns.
The Pipeline Execution Time Formula
For a k-stage pipeline executing N instructions, the total number of cycles needed is (N + k − 1). This is because the first instruction takes k cycles to fill the pipeline, and each subsequent instruction adds just 1 more cycle.
Total time = (N + k − 1) × cycle time
Substituting values where N = 1000, k = 5, and cycle time = 260 ns:
Total time = (1000 + 5 − 1) × 260 = 1004 × 260 = 261,040 ns
Converting to microseconds: 261,040 ÷ 1000 = 261.04 µs
Formula used: Tpipeline = (N + k − 1) × (tmax + tlatch)
The correct answer is 261.04 µs.

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