Computer Sciences > GATE 2025 SET-1 > CPU Datapath
A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?
A
The data path can implement arithmetic operations involving two registers.
B
The data path can implement arithmetic operations involving one register and one immediate value.
C
The data path can implement arithmetic operations involving two immediate values.
D
The data path can only implement arithmetic operations involving one register and one immediate value.

Correct : a,b,c

Explanation:
1. Analyze the Input Multiplexers (Mux_A and Mux_B):
The diagram shows that the inputs to the ALU are fully controlled by two independent multiplexers, Mux_A and Mux_B:
Mux_A Inputs: Can choose between register RA (32 bit) OR an immediate value 32 bit.
Mux_B Inputs: Can choose between register RB (32 bit) OR an immediate value 32 bit.

2. Evaluate the Combinations:
Because the select lines (Select RA/immediate and Select RB/immediate) work independently of each other, we can configure them to route different combinations of variables straight to the ALU:

Combination 1 (Two Registers): Set Mux_A to select RA and Mux_B to select RB. This allows arithmetic operations involving two registers. (Statement a is True)
Combination 2 (One Register, One Immediate): Set Mux_A to select RA and Mux_B to select its immediate value (or vice versa). This allows arithmetic operations involving one register and one immediate value. (Statement b is True)
Combination 3 (Two Immediate Values): Set both Mux_A and Mux_B to select their respective immediate values. This allows arithmetic operations involving two immediate values simultaneously. (Statement c is True)

3. Evaluate Statement (d):
• Statement (d) claims that the data path can only implement operations between one register and one immediate value. Since we proved it can handle two registers or two immediate values as well, this statement is False.

4. Conclusion:
Statements (a), (b), and (c) are all completely valid configurations supported by the provided multiplexer layout.

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