Computer Sciences > GATE 2024 SET-2 > Direct Memory Access (DMA)
Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?
A
2,56,000
B
3,200
C
25,60,000
D
32,000

Correct : c

To find the data transfer rate of the DMA controller, let us calculate the number of bytes transferred per second step-by-step:
Processor Clock Frequency: The processor operates at 4 MHz, which means it runs at a total of 4,000,000 cycles per second.
Cycles Allocated for DMA: The DMA controller uses 1% of these processor cycles for cycle stealing:
    DMA cycles per second = 1% of 4,000,000 = 40,000 cycles/sec
Bytes Transferred per Cycle: The DMA controller transfers 8 bytes of data in 1 cycle.
Total Data Transferred in Bytes:
    Data rate in bytes = 40,000 cycles/sec × 8 bytes/cycle = 320,000 bytes/sec
Convert Bytes to Bits: Since 1 byte contains 8 bits, we multiply the total bytes by 8 to get the rate in bits per second (bps):
    Data transfer rate = 320,000 × 8 = 2,560,000 bits per second (25,60,000)

Thus, the correct data transfer rate of the DMA controller is 25,60,000 bits per second, matching option (c).

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DMA controller data transfer rate GATE computer science 2024 processor cycles DMA cycle stealing DMA data transfer rate bits per second computer science gate DMA usage percentage computer sciences gate byte to bit conversion

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