Computer Sciences > GATE 2023 > Computer Architecture
Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle. The total execution time for executing 100 instructions on this processor is _______ ns.
Correct : 2140
Similar Questions
An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2 Consider the following sequence of ins...
A palindrome is a word that reads the same forwards and backwards. In a game
of words, a player has the following two plates painted with letters.
From...
Which number does not belong in the series below?
2, 5, 10, 17, 26, 37, 50, 64
Total Unique Visitors
Loading......