Computer Sciences > Gate 2022 > LRU Algorithm
Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?
A
Each cache block in WB and WT has a dirty bit.
B
Every write hit in WB leads to a data transfer from cache to main memory.
C
Eviction of a block from WT will not lead to data transfer from cache to main memory.
D
A read miss in WB will never lead to eviction of a dirty block from WB.

Correct : a,b,d

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