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A certain processor uses a fully associative cache of size 16 kB, The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?
A
24 bits and 0 bits
B
28 bits and 4 bits
C
24 bits and 4 bits
D
28 bits and 0 bits

Correct : d

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cache design GATE 2019 fully associative cache tag index bits cache block size main memory address computer science gate cache design question byte addressable memory cache tag index

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