Computer Sciences > Gate 2017 Set-1 > Cache Memory
Consider a 2-way set associative cache with 256 blocks and uses LRU replacement, Initially the cache is empty. Conflict misses are those misses which occur due the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks
(0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129)
is repeated 10 times. The number of conflict misses experienced by the cache is ___________.Correct : 76
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