Computer Sciences > Gate 2017 Set-1 > Pipelining
Instruction execution in a processor is divided into 5 stages.
Instruction Fetch(IF), Instruction Decode (ID), Operand Fetch(OF), Execute(EX), and Write Back(WB),
These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:

(i) a naïve pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage id divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.


The speedup (correct to two decimals places) achieved by EP over NP in executing 20 independent instructions with no hazards is ________________.

Correct : 1.50-1.51

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pipelined processor design instruction pipeline stages GATE computer science 2017 pipelining in processors speedup calculation NP vs EP independent instructions execution pipeline efficiency nanoseconds delay OF stage division GATE computer science questions

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