The TLB performs an associative search in parallel on all its valid entries using the page number of the incoming virtual addresses.

If the virtual address of a word given by the CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory

The memory access time using a given inverted page table is always the same for all incoming virtual addresses.

In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same.