Biomedical Engineering > GATE 2026 > Gate-level Timing Analysis
In the following digital circuit, the delay of both the NAND gates is 4 nanoseconds (ns) and the delay of the NOT gate is 1 ns. If a 10 MHz clock signal with 50% duty cycle is provided as the input, the duty cycle of the output is _________% (Answer in integer)
Correct : 53
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