Biomedical Engineering > GATE 2022 > Digital Circuits
In the circuit diagram shown below, the logic gates operate with a supply voltage of 1 V. NAND and XNOR have 200 ps and 400 ps input-to-output delay, respectively.
At time t=T, A(t)=0, B(t)=1 and Z(t)=0. When the inputs are changed to A(t)=1, B(t)=0 at t=2T, a 1 V pulse is observed at Z. The pulse width of the 1 V pulse is _______ ps.
At time t=T, A(t)=0, B(t)=1 and Z(t)=0. When the inputs are changed to A(t)=1, B(t)=0 at t=2T, a 1 V pulse is observed at Z. The pulse width of the 1 V pulse is _______ ps.
Explanation
Correct : b
Similar Questions
What is the worst-case time complexity of insertion in an AVL tree?
Which operations on a binary search tree have O(h) complexity?
Compare search complexities of sorted array vs balanced BST.